In recent years, development of a ferroelectric memory (FeRAM) retaining information in a ferroelectric capacitor by making use of a polarization inversion of a ferroelectric substance has been in progress. The ferroelectric memory is a nonvolatile memory in which retained information does not disappear even when power is turned off, and a high integration, a high-speed driving, a high durability, and a low power consumption can be realized.
As a material of a ferroelectric film constituting the ferroelectric capacitor, a ferroelectric oxide having a perovskite crystal structure such as PZT (Pb (Zr, Ti) O3), SBT (SrBi2Ta2O9) whose amount of remanent polarization is large has been mainly used. The amount of remanent polarization of PZT is approximately 10 μC/cm2 to 30 μC/cm2. However, characteristics of the ferroelectric film are likely to be deteriorated by moisture penetrating from outside through an interlayer insulating film, such as a silicon oxide film, having high affinity with water. That is, in performing a high temperature process such as forming the interlayer insulating film or metal wirings, the moisture is decomposed to hydrogen and oxygen, and this hydrogen penetrates into the ferroelectric film to react with oxygen constituting the ferroelectric film, resulting that oxygen deficiency in the ferroelectric film is caused. As a result, crystallinity of the ferroelectric film is lowered.
Further, after the ferroelectric capacitor is formed, an interlayer insulating film covering the ferroelectric capacitor is formed. In forming the interlayer insulating film, a plasma CVD method using TEOS, a high density plasma method or the like is applied. Thus, in forming the interlayer insulating film, the ferroelectric capacitor is exposed to plasma, resulting that a characteristic thereof is deteriorated. There exists an art in which a protective film such as an aluminum oxide film covers a ferroelectric capacitor, and then an interlayer insulating film is formed, but, it is also difficult to hold the characteristic sufficiently by this art.
Further, after the interlayer insulating film is formed, an opening reaching an electrode of the ferroelectric capacitor is formed, and a wiring connecting to the electrode is formed. In forming the opening, etching in which plasma is used is performed. Thus, in forming the opening as well, the ferroelectric capacitor is exposed to plasma, resulting that a characteristic thereof is deteriorated.
Accordingly, in manufacturing the ferroelectric memory provided with the ferroelectric capacitor, steps where deterioration of the characteristic of the ferroelectric capacitor formed already is unavoidable are included. Thus, conventionally, oxygen is supplied to the ferroelectric capacitor, and thereby annealing (recovery annealing) that recovers the characteristic has been performed. It is important to diffuse oxygen into the ferroelectric film sufficiently in this recovery annealing.
Here, a conventional manufacturing method of a planar-type ferroelectric memory will be explained. FIG. 8A to FIG. 8L are cross-sectional views showing the conventional manufacturing method of the planar-type ferroelectric memory in order of steps.
First, as illustrated in FIG. 8A, an element isolation insulating film 102 is formed on a surface of a semiconductor substrate 101 composed of silicon or the like. Next, an ion implantation of B (boron) is performed in the surface of an element region demarcated by the element isolation insulating film 102 thereby forming a P-well 103. Next, gate insulating films 104 and gate electrodes 105 are formed on the P-well 103. Thereafter, an ion implantation of P (phosphorus) is performed in the surface of the P-well 103 thereby forming shallow impurity diffusion layers 106. Subsequently, sidewall insulating films 107 are formed on lateral sides of the gate electrodes 105. Next, an ion implantation of As (arsenic) is performed in the surface of the P-well 103 thereby forming deep impurity diffusion layers 108. Thus, transistors Tr are formed. Note that the single transistor Tr includes the two impurity diffusion layers 108, and one of them is shared with another transistor Tr. The impurity diffusion layer 108 that is shared constitutes a drain, and the impurity diffusion layer 108 that is not shared constitutes a source.
Next, as illustrated in FIG. 8B, a silicon oxynitride film 111 covering the transistors Tr is formed, and an NSG film 112 is formed thereon by using TEOS. Next, the surface of the NSG film 112 is flattened.
Thereafter, as illustrated in FIG. 8C, an NSG film 116 is formed on the NSG film 112 by using TEOS, and then a dehydration treatment thereof is performed. Next, an aluminum oxide film 117 is formed on the NSG film 116, and then a heat treatment (RTA) is performed.
Next, as illustrated in FIG. 8D, a platinum film 118, a PZT film 119, and an iridium oxide film 120 are formed sequentially on the aluminum oxide film 117. A heat treatment (RTA) is performed between forming the PZT film 119 and forming the iridium oxide film 120. Further, the iridium oxide film 120 has a two-layer structure, and a heat treatment (RTA) is also performed after the lower layer is formed.
Thereafter, as illustrated in FIG. 8E, the iridium oxide film 120 is patterned, and then recovery annealing is performed. Subsequently, the PZT film 119 is patterned, and then recovery annealing is performed. Next, an aluminum oxide film 121 is formed on the entire surface, and then recovery annealing is performed.
Subsequently, as illustrated in FIG. 8F, the aluminum oxide film 121 and the platinum film 118 are patterned. Thus, ferroelectric capacitors C are formed. Thereafter, recovery annealing is performed. Further, an aluminum oxide film 122 is formed on the entire surface, and then recovery annealing is performed. Subsequently, an NSG film 123 is formed on the aluminum oxide film 122 by using TEOS, and then the surface thereof is flattened.
Next, plasma annealing is performed in a nitrogen atmosphere, so that the surface of the NSG film 123 is nitrided. Next, as illustrated in FIG. 8G, a resist pattern 191 having openings at predetermined positions is formed on the NSG film 123. Then, etching of the NSG film 123 and so on is performed by using the resist pattern 191 as a mask thereby forming contact holes 113s reaching the sources and a contact hole 113d reaching the drain.
Subsequently, as illustrated in FIG. 8H, the resist pattern 191 is removed. Next, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film (not-illustrated) is formed thereon. Then, the tungsten film and the barrier metal film are polished until the NSG film 123 is exposed. As a result, contact plugs 114s are formed in the contact holes 113s, and a contact plug 114d is formed in the contact hole 113d. Next, plasma annealing is performed in a nitrogen atmosphere, so that the surface of the NSG film 123 is nitrided. Thereafter, a silicon oxynitride film 115 is formed on the NSG film 123.
Next, as illustrated in FIG. 8I, a resist pattern 192 having openings at predetermined positions is formed on the silicon oxynitride film 115. Then, etching of the silicon oxynitride film 115 and so on is performed by using the resist pattern 192 as a mask thereby forming contact holes 127t reaching top electrodes (the iridium oxide film 120) and contact holes 127b reaching bottom electrodes (the platinum film 118).
Thereafter, as illustrated in FIG. 8J, the resist pattern 192 is removed, and then recovery annealing is performed.
Subsequently, as illustrated in FIG. 8K, the silicon oxynitride film 115 is removed by performing etching back.
Next, as illustrated in FIG. 8L, wirings 130 in contact with the contact plugs 114s and 114d, the top electrodes (the iridium oxide film 120), and the bottom electrodes (the platinum film 118) are formed. Thereafter, a heat treatment is performed in a nitrogen atmosphere. Subsequently, an aluminum oxide film 131 is formed on the entire surface. Thereafter, upper layer wirings and so on are formed.
Next, a conventional manufacturing method of a stack-type ferroelectric memory will be explained. FIG. 9A to FIG. 9L are cross-sectional views showing the conventional manufacturing method of the stack-type ferroelectric memory in order of steps.
First, similarly to the case of manufacturing the planar-type ferroelectric memory, as illustrated in FIG. 9A, the processes to flattening the NSG film 112 are performed. Next, a dehydration treatment of the NSG film 112 is performed.
Next, as illustrated in FIG. 9B, a resist pattern 196 having openings at predetermined positions is formed on the NSG film 112. Then, etching of the NSG film 112 and so on is performed by using the resist pattern 196 as a mask thereby forming contact holes 151s reaching the sources and a contact hole 151d reaching the drain.
Subsequently, as illustrated in FIG. 9C, the resist pattern 196 is removed. Next, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film (not-illustrated) is formed thereon. Then, the tungsten film and the barrier metal film are polished until the NSG film 112 is exposed. As a result, contact plugs 152s are formed in the contact holes 151s, and a contact plug 152d is formed in the contact hole 151d. Next, plasma annealing is performed in a nitrogen atmosphere, so that the surface of the NSG film 112 is nitrided.
Next, as illustrated in FIG. 9D, a silicon oxynitride film 153 and an NSG film 154 are formed on the NSG film 112 sequentially.
Next, as illustrated in FIG. 9E, a resist pattern 195 having openings at predetermined positions is formed on the NSG film 154. Then, etching of the NSG film 154 and so on is performed by using the resist pattern 195 as a mask thereby forming contact holes 156s reaching the contact plugs 152s. 
Thereafter, as illustrated in FIG. 9F, the resist pattern 195 is removed.
Subsequently, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film (not-illustrated) is formed thereon.
Then, the tungsten film and the barrier metal film are polished until the NSG film 154 is exposed. As a result, as illustrated in FIG. 9G, contact plugs 157s are formed in the contact holes 156s. Next, plasma annealing is performed in a nitrogen atmosphere, so that the surface of the NSG film 154 is nitrided.
Next, as illustrated in FIG. 9H, a bottom electrode film 158, a PZT film 159, and a top electrode film 160 are formed on the NSG film 154 sequentially. In forming the bottom electrode film 158, a titanium film, a titanium aluminum nitride film, and an iridium film are formed sequentially. Further, in forming the top electrode film 160, after an iridium oxide film is formed, a heat treatment (RTA) is performed, and then another iridium oxide film is formed. Thereafter, another heat treatment (RTA) is performed.
Thereafter, as illustrated in FIG. 9I, a platinum film 161, a titanium nitride film 162, and an NSG film 163 are formed on the top electrode film 160 sequentially.
Subsequently, as illustrated in FIG. 9J, a resist pattern 197 covering regions where ferroelectric capacitors are desired to be formed is formed on the NSG film 163.
Next, as illustrated in FIG. 9K, patterning of the NSG film 163 is performed by using the resist pattern 197 as a mask.
Next, as illustrated in FIG. 9L, patterning of the titanium nitride film 162 is performed by using the resist pattern 197 and the NSG film 163 as a mask. The resist pattern 197 disappears while performing this patterning.
Thereafter, as illustrated in FIG. 9M, the platinum film 161, the top electrode film 160, the PZT film 159, and the bottom electrode film 158 are patterned collectively by using the NSG film 163 and the titanium nitride film 162 as a mask. Thus, ferroelectric capacitors C are formed.
Subsequently, as illustrated in FIG. 9N, the NSG film 163 and the titanium nitride film 162 used as a hard mask are removed, and then recovery annealing is performed.
Next, as illustrated in FIG. 9O, an aluminum oxide film 164 is formed on the entire surface. The aluminum oxide film 164 has a two-layer structure, and after the lower layer is formed, a heat treatment (RTA) is performed.
Next, as illustrated in FIG. 9P, a silicon oxide film 165 is formed on the entire surface by a high density plasma CVD method, and then the surface thereof is flattened. Thereafter, a resist pattern 198 having an opening at a predetermined position is formed on the silicon oxide film 165. Then, etching of the silicon oxide film 165 and so on is performed by using the resist pattern 198 as a mask thereby forming a contact hole 166d reaching the contact plug 152d. 
Subsequently, as illustrated in FIG. 9Q, the resist pattern 198 is removed. Next, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film (not-illustrated) is formed thereon. Then, the tungsten film and the barrier metal film are polished until the silicon oxide film 165 is exposed. As a result, a contact plug 167d is formed in the contact hole 166d. 
Next, as illustrated in FIG. 9R, a silicon oxynitride film 168 is formed on the silicon oxide film 165.
Thereafter, as illustrated in FIG. 9S, a resist pattern 199 having openings at predetermined positions is formed on the silicon oxynitride film 168. Then, etching of the silicon oxynitride film 168 and so on is performed by using the resist pattern 199 as a mask thereby forming contact holes 169t reaching the platinum film 161.
Subsequently, as illustrated in FIG. 9T, the resist pattern 199 is removed, and then recovery annealing is performed. Thereafter, the silicon oxynitride film 168 is removed by performing etching back.
Next, as illustrated in FIG. 9U, a barrier metal film (not-illustrated) is formed on the entire surface, and a tungsten film (not-illustrated) is formed thereon. Then, the tungsten film and the barrier metal film are polished until the silicon oxide film 165 is exposed. As a result, contact plugs 170t are formed in the contact holes 169t. 
Next, as illustrated in FIG. 9V, wirings 171 in contact with the contact plugs 167s and 170t are formed. Thereafter, a heat treatment is performed in a nitrogen atmosphere. Subsequently, an aluminum oxide film 172 is formed on the entire surface. Thereafter, upper layer wirings and so on are formed.
However, in these conventional methods, there is a case that recovery annealing of the ferroelectric capacitor cannot be performed sufficiently. This is because the contact hole reaching the top electrode is small and oxygen supply is not sufficient. If the contact hole is made to be large, it is possible to increase the supply amount of oxygen, but in this case, the distance between the adjacent contact holes narrows. Therefore, problems such as a short circuit are likely to be caused when positional displacement occurs in the wirings formed thereon. Further, as illustrated in FIG. 8L, when positional displacement occurs in the method where the wirings 130 are also formed in the contact holes 127t and 127b, there arises a case that the iridium oxide film 120 and the platinum film 118 are etched. In this manner, if the contact hole is simply made to be large, a positional displacement margin in forming the wirings becomes small.
Note that Patent Documents 1 and 2 disclose that a contact hole is made to be large, but a problem in which the positional displacement margin as described above is decreased is left.
Patent Document 1: Japanese Patent No. 3331334
Patent Document 2: Japanese Laid-open Patent Publication No. 2001-358309